feat: Enhance MMU by separating sections and configuring permissions

.vscode/launch.json

@@ -33,6 +33,31 @@
       ],
       "preLaunchTask": "Run QEMU"
     },
+    {
+      "name": "Attach to QEMU (AArch64) wo. window",
+      "type": "cppdbg",
+      "request": "launch",
+      "program": "${workspaceFolder}/target/aarch64-unknown-none/debug/nova",
+      "miDebuggerServerAddress": "localhost:1234",
+      "miDebuggerPath": "gdb",
+      "cwd": "${workspaceFolder}",
+      "stopAtEntry": true,
+      "externalConsole": false,
+      "MIMode": "gdb",
+      "setupCommands": [
+        {
+          "description": "Enable pretty-printing for gdb",
+          "text": "-enable-pretty-printing",
+          "ignoreFailures": true
+        },
+        {
+          "description": "Show assembly on stop",
+          "text": "set disassemble-next-line on",
+          "ignoreFailures": true
+        }
+      ],
+      "preLaunchTask": "Run QEMU wo window"
+    },
 
     {
       "name": "Attach LLDB",

.vscode/tasks.json

@@ -14,9 +14,38 @@
     {
       "label": "Run QEMU",
       "type": "shell",
-      "command": "llvm-objcopy -O binary target/aarch64-unknown-none/debug/nova target/aarch64-unknown-none/debug/kernel8.img && qemu-system-aarch64 -M raspi3b -cpu cortex-a53 -serial stdio -sd sd.img -kernel ${workspaceFolder}/target/aarch64-unknown-none/debug/kernel8.img -S -s -m 1024",
+      "command": "llvm-objcopy -O binary target/aarch64-unknown-none/debug/nova target/aarch64-unknown-none/debug/kernel8.img && echo Starting QEMU&qemu-system-aarch64 -M raspi3b -cpu cortex-a53 -serial stdio -sd sd.img -kernel ${workspaceFolder}/target/aarch64-unknown-none/debug/kernel8.img -S -s -m 1024",
       "isBackground": true,
-      "dependsOn": ["Build"]
+      "dependsOn": ["Build"],
+      "problemMatcher": {
+                "pattern": {
+                    "regexp": "^(Starting QEMU)",
+                    "line": 1,
+                },
+                "background": {
+                    "activeOnStart": true,
+                    "beginsPattern": "^(Starting QEMU)",
+                    "endsPattern": "^(Starting QEMU)"
+                }
+            }
+    },
+        {
+      "label": "Run QEMU wo window",
+      "type": "shell",
+      "command": "llvm-objcopy -O binary target/aarch64-unknown-none/debug/nova target/aarch64-unknown-none/debug/kernel8.img && echo Starting QEMU&qemu-system-aarch64 -M raspi3b -cpu cortex-a53 -display none -serial stdio -sd sd.img -kernel ${workspaceFolder}/target/aarch64-unknown-none/debug/kernel8.img -S -s -m 1024",
+      "isBackground": true,
+      "dependsOn": ["Build"],
+      "problemMatcher": {
+                "pattern": {
+                    "regexp": "^(Starting QEMU)",
+                    "line": 1,
+                },
+                "background": {
+                    "activeOnStart": true,
+                    "beginsPattern": "^(Starting QEMU)",
+                    "endsPattern": "^(Starting QEMU)"
+                }
+            }
     }
   ]
 }

README.md

@@ -14,8 +14,9 @@ NovaOS is a expository project where I build a kernel from scratch for a Raspber
 - Communicate with peripherals via mailboxes ✓
 - Frame Buffer ✓
 - Heap Memory allocation ✓
+- MMU
+- SVC instructions
 - Multi Core
 - Dynamic clock speed
-- MMU
 - Multiprocessing
 - Basic Terminal over UART

link.ld

@@ -10,7 +10,7 @@ SECTIONS {
         *(.rodata .rodata.*)
     }
 
-    .data : {
+    .data ALIGN(2M) : {
         _data = .;
         *(.data .data.*)
     }
@@ -27,28 +27,28 @@ SECTIONS {
         KEEP(*(.vector_table))
     }
 
-    .heap : ALIGN(16)
-    {
+    .heap ALIGN(16): {
     __heap_start = .;
-    . += 0x10000; #10kB
+    . += 100K; #100kB
     __heap_end = .;
     }
 
-    .stack : ALIGN(16)
-    {
+    .stack ALIGN(16): {
     __stack_start = .;
-    . += 0x10000; #10kB stack
+    . += 10K; #10kB stack
     __stack_end = .;
     }
 
-    .stack_el0 : ALIGN(16)
-    {
+    . = ALIGN(2M);
+
+    __kernel_end = .;
+
+    .stack_el0 : {
     __stack_start_el0 = .;
-    . += 0x10000; #10kB stack
+    . += 10K; #10kB stack
     __stack_end_el0 = .;
     }
 
-
     _end = .;
 }
 

src/aarch64/mmu.rs

@@ -1,17 +1,161 @@
-use core::arch::asm;
+use core::u64::MAX;
 
-pub fn init_mmu() {
-    let ips = 0b000 << 32;
+use nova_error::NovaError;
 
-    // 4KB granularity
-    let tg0 = 0b00 << 14;
-    let tg1 = 0b00 << 30;
+use crate::{println, PERIPHERAL_BASE};
 
-    //64-25 = 29 bits of VA
-    // FFFF_FF80_0000_0000 start address
-    let t0sz = 25;
-
-    let tcr_el1: u64 = ips | tg0 | tg1 | t0sz;
-
-    unsafe { asm!("msr TCR_EL1, {0:x}", in(reg) tcr_el1) };
+unsafe extern "C" {
+    static mut __translation_table_l2_start: u64;
+    static __stack_start_el0: u64;
+    static __kernel_end: u64;
+    static _data: u64;
+}
+
+const BLOCK: u64 = 0b01;
+const TABLE: u64 = 0b11;
+
+const EL0_ACCESSIBLE: u64 = 1 << 6;
+
+const WRITABLE: u64 = 0 << 7;
+const READ_ONLY: u64 = 1 << 7;
+
+const ACCESS_FLAG: u64 = 1 << 10;
+const INNER_SHAREABILITY: u64 = 0b11 << 8;
+
+const NORMAL_MEM: u64 = 0 << 2;
+const DEVICE_MEM: u64 = 1 << 2;
+
+/// Disallow EL1 Execution.
+const PXN: u64 = 1 << 53;
+
+/// Disallow EL0 Execution.
+const UXN: u64 = 1 << 54;
+
+const GRANULARITY: usize = 4 * 1024;
+const TABLE_ENTRY_COUNT: usize = GRANULARITY / size_of::<u64>(); // 2MiB
+const LEVEL2_BLOCK_SIZE: usize = TABLE_ENTRY_COUNT * GRANULARITY;
+
+const MAX_PAGE_COUNT: usize = 1 * 1024 * 1024 * 1024 / GRANULARITY;
+#[repr(align(4096))]
+pub struct PageTable([u64; TABLE_ENTRY_COUNT]);
+
+#[no_mangle]
+pub static mut TRANSLATIONTABLE_TTBR0: PageTable = PageTable([0; 512]);
+pub static mut TRANSLATIONTABLE_TTBR0_L2_0: PageTable = PageTable([0; 512]);
+
+static mut PAGING_BITMAP: [u64; MAX_PAGE_COUNT / 64] = [0; MAX_PAGE_COUNT / 64];
+
+pub fn init_translation_table() {
+    unsafe {
+        TRANSLATIONTABLE_TTBR0.0[0] =
+            table_descriptor_entry(&raw mut TRANSLATIONTABLE_TTBR0_L2_0 as usize);
+        println!("{}", &raw mut TRANSLATIONTABLE_TTBR0_L2_0 as u64);
+        println!("{}", TRANSLATIONTABLE_TTBR0.0[0] & 0x0000_FFFF_FFFF_F000);
+
+        for i in 0..512 {
+            let addr = 0x0 + (i * LEVEL2_BLOCK_SIZE);
+
+            if addr < &_data as *const _ as usize {
+                let _ = alloc_block_l2(
+                    addr,
+                    &TRANSLATIONTABLE_TTBR0,
+                    EL0_ACCESSIBLE | READ_ONLY | NORMAL_MEM,
+                );
+            } else if addr < &__kernel_end as *const _ as usize {
+                let _ = alloc_block_l2(addr, &TRANSLATIONTABLE_TTBR0, WRITABLE | UXN | NORMAL_MEM);
+            } else if addr < PERIPHERAL_BASE {
+                let _ = alloc_block_l2(
+                    addr,
+                    &TRANSLATIONTABLE_TTBR0,
+                    EL0_ACCESSIBLE | WRITABLE | PXN | NORMAL_MEM,
+                );
+            } else {
+                let _ = alloc_block_l2(
+                    addr,
+                    &TRANSLATIONTABLE_TTBR0,
+                    EL0_ACCESSIBLE | WRITABLE | UXN | PXN | DEVICE_MEM,
+                );
+            };
+        }
+        println!("Done");
+    }
+}
+
+pub fn alloc_page() -> Result<usize, NovaError> {
+    find_unallocated_page()
+}
+
+fn find_unallocated_page() -> Result<usize, NovaError> {
+    for (i, entry) in unsafe { PAGING_BITMAP }.iter().enumerate() {
+        if *entry != u64::MAX {
+            for offset in 0..64 {
+                if entry >> offset & 0b1 == 0 {
+                    return Ok((i * 64 + offset) * GRANULARITY);
+                }
+            }
+        }
+    }
+    Err(NovaError::Paging)
+}
+
+pub fn alloc_block_l2(
+    virtual_addr: usize,
+    base_table: &PageTable,
+    additional_flags: u64,
+) -> Result<(), NovaError> {
+    let physical_address = find_unallocated_block_l2()?;
+
+    let l2_off = virtual_addr / GRANULARITY / TABLE_ENTRY_COUNT;
+    let l1_off = l2_off / TABLE_ENTRY_COUNT;
+
+    let l2_table =
+        unsafe { &mut *((base_table.0[l1_off] & 0x0000_FFFF_FFFF_F000) as *mut PageTable) };
+
+    let new_entry = create_block_descriptor_entry(physical_address, additional_flags);
+
+    l2_table.0[l2_off] = new_entry;
+
+    allocate_block_l2(physical_address);
+
+    Ok(())
+}
+
+fn find_unallocated_block_l2() -> Result<usize, NovaError> {
+    let mut count = 0;
+    for (i, entry) in unsafe { PAGING_BITMAP }.iter().enumerate() {
+        if *entry == 0 {
+            count += 1;
+        } else {
+            count = 0;
+        }
+
+        if count == 8 {
+            return Ok((i - 7) * 64 * GRANULARITY);
+        }
+    }
+    Err(NovaError::Paging)
+}
+
+fn allocate_block_l2(physical_address: usize) {
+    let page = physical_address / GRANULARITY;
+    for i in 0..8 {
+        unsafe { PAGING_BITMAP[(page / 64) + i] = MAX };
+    }
+}
+
+fn create_block_descriptor_entry(addr: usize, additional_flags: u64) -> u64 {
+    let pxn = 0 << 53; // Privileged execute never
+    let uxn = 0 << 54; // Unprivileged execute never
+
+    (addr as u64 & 0x0000_FFFF_FFE0_0000)
+        | BLOCK
+        | ACCESS_FLAG
+        | pxn
+        | uxn
+        | INNER_SHAREABILITY
+        | additional_flags
+}
+
+pub fn table_descriptor_entry(addr: usize) -> u64 {
+    0 | (addr as u64 & 0x0000_FFFF_FFFF_F000) | TABLE
 }

src/aarch64/registers.rs

@@ -52,6 +52,8 @@ psr!(SPSR_EL1, u32);
 
 psr!(ELR_EL1, u32);
 
+psr!(SCTLR_EL1, u32);
+
 pub fn read_exception_source_el() -> u32 {
     read_spsr_el1() & 0b1111
 }

src/configuration.rs

@@ -1,16 +1,33 @@
-static SCTLR_EL1_MMU_DISABLED: u64 = 0; //M
-static SCTLR_EL1_DATA_CACHE_DISABLED: u64 = 0 << 2; //C
-static SCTLR_EL1_INSTRUCTION_CACHE_DISABLED: u64 = 0 << 12; //I
-static SCTLR_EL1_LITTLE_ENDIAN_EL0: u64 = 0 << 24; //E0E
-static SCTLR_EL1_LITTLE_ENDIAN_EL1: u64 = 0 << 25; //EE
+const SCTLR_EL1_MMU_ENABLED: u64 = 1; //M
+const SCTLR_EL1_DATA_CACHE_DISABLED: u64 = 0 << 2; //C
+const SCTLR_EL1_INSTRUCTION_CACHE_DISABLED: u64 = 0 << 12; //I
+const SCTLR_EL1_LITTLE_ENDIAN_EL0: u64 = 0 << 24; //E0E
+const SCTLR_EL1_LITTLE_ENDIAN_EL1: u64 = 0 << 25; //EE
+const SCTLR_EL1_SPAN: u64 = 1 << 23; //SPAN
 
 #[allow(clippy::identity_op)]
-static SCTLR_EL1_RES: u64 = (0 << 6) | (1 << 11) | (0 << 17) | (1 << 20) | (1 << 22); //Res0 & Res1
+const SCTLR_EL1_RES: u64 = (0 << 6) | (1 << 11) | (0 << 17) | (1 << 20) | (1 << 22); //Res0 & Res1
 
 #[no_mangle]
-pub static SCTLR_EL1_CONF: u64 = SCTLR_EL1_MMU_DISABLED
+pub static SCTLR_EL1_CONF: u64 = SCTLR_EL1_MMU_ENABLED
     | SCTLR_EL1_DATA_CACHE_DISABLED
     | SCTLR_EL1_INSTRUCTION_CACHE_DISABLED
     | SCTLR_EL1_LITTLE_ENDIAN_EL0
     | SCTLR_EL1_LITTLE_ENDIAN_EL1
-    | SCTLR_EL1_RES;
+    | SCTLR_EL1_RES
+    | SCTLR_EL1_SPAN;
+
+const TG0: u64 = 0b00 << 14; // 4KB granularity EL0
+const T0SZ: u64 = 25; // 25 Bits of TTBR select -> 39 Bits of VA
+const SH0: u64 = 0b11 << 12; // Inner shareable
+
+const TG1: u64 = 0b10 << 30; // 4KB granularity EL1
+const T1SZ: u64 = 25 << 16; // 25 Bits of TTBR select -> 39 Bits of VA
+const EPD1: u64 = 0b1 << 23; // Trigger translation fault when using TTBR1_EL1
+const SH1: u64 = 0b11 << 28; // Inner sharable
+
+const IPS: u64 = 0b000 << 32; // 32 bits of PA space -> up to 4GiB
+const AS: u64 = 0b1 << 36; // configure an ASID size of 16 bits
+
+#[no_mangle]
+pub static TCR_EL1_CONF: u64 = IPS | TG0 | TG1 | T0SZ | T1SZ | SH0 | SH1 | EPD1 | AS;

src/interrupt_handlers.rs

@@ -5,7 +5,7 @@ use alloc::vec::Vec;
 use crate::{
     aarch64::registers::{
         daif::{mask_all, unmask_irq},
-        read_esr_el1, read_exception_source_el,
+        read_elr_el1, read_esr_el1, read_exception_source_el,
     },
     get_current_el,
     peripherals::{
@@ -118,15 +118,17 @@ unsafe extern "C" fn rust_synchronous_interrupt_imm_lower_aarch64() {
     println!("--------Sync Exception in EL{}--------", source_el);
     println!("Exception escalated to EL {}", get_current_el());
     println!("Current EL: {}", get_current_el());
-    let esr = EsrElX::from(read_esr_el1());
-    println!("{:?}", EsrElX::from(esr));
-    println!("Return register address: {:#x}", read_esr_el1());
+    let esr: EsrElX = EsrElX::from(read_esr_el1());
+    println!("{:?}", esr);
+    println!("Return address: {:#x}", read_elr_el1());
 
     match esr.ec {
         0b100100 => {
             println!("Cause: Data Abort from a lower Exception level");
         }
-        _ => {}
+        _ => {
+            println!("Unknown Error Code: {:b}", esr.ec);
+        }
     }
     println!("-------------------------------------");
 
@@ -136,7 +138,9 @@ unsafe extern "C" fn rust_synchronous_interrupt_imm_lower_aarch64() {
 fn clear_interrupt_for_source(source: IRQSource) {
     match source {
         IRQSource::UartInt => clear_uart_interrupt_state(),
-        _ => {}
+        _ => {
+            todo!()
+        }
     }
 }
 
@@ -212,6 +216,7 @@ pub fn get_irq_pending_sources() -> u64 {
     pending
 }
 
+#[inline(always)]
 pub fn initialize_interrupt_handler() {
     unsafe { INTERRUPT_HANDLERS = Some(Vec::new()) };
 }

src/lib.rs

@@ -14,7 +14,7 @@ use heap::Heap;
 
 use crate::{interrupt_handlers::initialize_interrupt_handler, logger::DefaultLogger};
 
-static PERIPHERAL_BASE: u32 = 0x3F00_0000;
+static PERIPHERAL_BASE: usize = 0x3F00_0000;
 
 unsafe extern "C" {
     unsafe static mut __heap_start: u8;

src/main.rs

@@ -12,11 +12,13 @@ extern crate alloc;
 
 use alloc::boxed::Box;
 use nova::{
-    aarch64::registers::{daif, read_id_aa64mmfr0_el1, read_tcr_el1},
+    aarch64::{
+        mmu::init_translation_table,
+        registers::{daif, read_id_aa64mmfr0_el1},
+    },
     framebuffer::{FrameBuffer, BLUE, GREEN, RED},
     get_current_el, init_heap,
     interrupt_handlers::{enable_irq_source, IRQSource},
-    log,
     peripherals::{
         gpio::{
             blink_gpio, gpio_pull_up, set_falling_edge_detect, set_gpio_function, GPIOFunction,
@@ -33,6 +35,7 @@ global_asm!(include_str!("vector.S"));
 extern "C" {
     fn el2_to_el1();
     fn el1_to_el0();
+    fn configure_mmu_el1();
     static mut __bss_start: u32;
     static mut __bss_end: u32;
 }
@@ -63,7 +66,14 @@ pub extern "C" fn main() -> ! {
     println!("Exception level: {}", get_current_el());
 
     unsafe {
-        asm!("mrs x0, SCTLR_EL1",);
+        init_heap();
+        init_translation_table();
+        configure_mmu_el1();
+    };
+
+    println!("AA64 {:064b}", read_id_aa64mmfr0_el1());
+
+    unsafe {
         el2_to_el1();
     }
 
@@ -82,14 +92,10 @@ unsafe fn zero_bss() {
 #[no_mangle]
 pub extern "C" fn kernel_main() -> ! {
     nova::initialize_kernel();
-    println!("Kernel Main");
     println!("Exception Level: {}", get_current_el());
     daif::unmask_all();
 
     unsafe {
-        init_heap();
-        println!("{:b}", read_id_aa64mmfr0_el1());
-        println!("{:b}", read_tcr_el1());
         el1_to_el0();
     };
 
@@ -121,12 +127,12 @@ pub extern "C" fn el0() -> ! {
 
     loop {
         let temp = mailbox::read_soc_temp([0]).unwrap();
-        log!("{} °C", temp[1] / 1000);
+        println!("{} °C", temp[1] / 1000);
 
         blink_gpio(SpecificGpio::OnboardLed as u8, 500);
 
         let b = Box::new([1, 2, 3, 4]);
-        log!("{:?}", b);
+        println!("{:?}", b);
     }
 }
 

src/peripherals/uart.rs

@@ -118,11 +118,13 @@ fn uart_fifo_enable(enable: bool) {
     unsafe { write_address(UART0_LCRH, lcrh) };
 }
 
+#[inline(always)]
 fn uart_enable_rx_interrupt() {
     unsafe { write_address(UART0_IMSC, UART0_IMSC_RXIM) };
 }
 
 /// Set UART word length and set FIFO status
+#[inline(always)]
 fn uart_set_lcrh(wlen: u32, enable_fifo: bool) {
     let mut value = (wlen & 0b11) << 5;
     if enable_fifo {
@@ -131,10 +133,12 @@ fn uart_set_lcrh(wlen: u32, enable_fifo: bool) {
     unsafe { write_address(UART0_LCRH, value) };
 }
 
+#[inline(always)]
 pub fn read_uart_data() -> char {
     (unsafe { read_address(UART0_DR) } & 0xFF) as u8 as char
 }
 
+#[inline(always)]
 pub fn clear_uart_interrupt_state() {
     unsafe {
         write_address(UART0_ICR, 1 << 4);

src/pi3/power_management.rs

@@ -3,7 +3,7 @@ use core::ptr::{read_volatile, write_volatile};
 use crate::PERIPHERAL_BASE;
 
 /// Power Management Base
-static PM_BASE: u32 = PERIPHERAL_BASE + 0x10_0000;
+static PM_BASE: u32 = PERIPHERAL_BASE as u32 + 0x10_0000;
 static PM_RSTC: u32 = PM_BASE + 0x1c;
 static PM_WDOG: u32 = PM_BASE + 0x24;
 

src/vector.S

@@ -1,5 +1,5 @@
 
-.global vector_table
+.global v_table
 .extern irq_handler
 
 .macro    ventry    label
@@ -21,12 +21,18 @@ vector_table:
 
     ventry synchronous_interrupt_imm_lower_aarch64
     ventry irq_handler
+    ventry .
+    ventry .
+
+    ventry .
+    ventry .
+    ventry .
+    ventry .
 
 
 .align 4
 .global el2_to_el1
 el2_to_el1:
-
     mov x0, #(1 << 31)
     msr HCR_EL2, x0
 
@@ -46,9 +52,13 @@ el2_to_el1:
     adr x0, vector_table
     msr VBAR_EL1, x0
 
-    // Disable MMU
-    ldr x0, =SCTLR_EL1_CONF
-    msr sctlr_el1, x0
+    isb
+
+    adrp x0, SCTLR_EL1_CONF
+    ldr  x1, [x0, :lo12:SCTLR_EL1_CONF]
+    msr SCTLR_EL1, x1
+
+    isb
 
     // SIMD should not be trapped
     mrs x0, CPACR_EL1
@@ -56,9 +66,38 @@ el2_to_el1:
     orr x0,x0, x1
     msr CPACR_EL1,x0
 
+    isb
+
     // Return to EL1
     eret
 
+.align 4
+.global configure_mmu_el1
+configure_mmu_el1:
+    // Configure MMU
+    adrp x0, TCR_EL1_CONF
+    ldr  x1, [x0, :lo12:TCR_EL1_CONF]
+    msr TCR_EL1, x1
+    isb
+
+    // MAIR0: Normal Mem.
+    // MAIR1: Device Mem.
+    mov x0, #0x04FF
+    msr MAIR_EL1, x0
+    isb
+
+    // Configure translation table
+    adrp x0, TRANSLATIONTABLE_TTBR0
+    add  x1, x0, :lo12:TRANSLATIONTABLE_TTBR0
+    msr TTBR0_EL1, x1
+    msr TTBR1_EL1, x1
+
+    tlbi vmalle1
+    dsb ish
+    isb
+
+    ret
+
 .align 4
 .global el1_to_el0
 el1_to_el0:
@@ -75,6 +114,8 @@ el1_to_el0:
     ldr x0, =__stack_end_el0
     msr SP_EL0, x0
 
+    isb
+
     // Return to EL0
     eret
 

tools/start_simulator.sh

@@ -1,3 +1,5 @@
+set -e
+
 cargo build --target aarch64-unknown-none --release
 cd "$(dirname "$0")"
 

tools/start_simulator_debug.sh

@@ -1,3 +1,5 @@
+set -e
+
 cargo build --target aarch64-unknown-none
 
 cd "$(dirname "$0")"

workspace/nova_error/src/lib.rs

@@ -8,4 +8,5 @@ pub enum NovaError {
     Mailbox,
     HeapFull,
     EmptyHeapSegmentNotAllowed,
+    Paging,
 }