mirror of
https://github.com/iceHtwoO/novaOS.git
synced 2026-04-17 04:32:27 +00:00
Implement blinking LED
This commit is contained in:
124
src/main.rs
124
src/main.rs
@@ -2,47 +2,17 @@
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#![no_std]
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#![feature(asm_experimental_arch)]
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use core::{
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arch::asm,
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fmt::{self, Write},
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panic::PanicInfo,
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};
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use core::panic::PanicInfo;
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use gpio::{pull_down_gpio47, pull_up_gpio47};
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mod gpio;
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mod uart;
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#[panic_handler]
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fn panic(_panic: &PanicInfo) -> ! {
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loop {}
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}
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const BAUD: u32 = 115200;
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const UART_CLK: u32 = 48_000_000;
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const UART0_DR: u32 = 0x3F20_1000;
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const UART0_FR: u32 = 0x3F20_1018;
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const UART0_FR_TXFF: u32 = 1 << 5;
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const UART0_IBRD: u32 = 0x3F20_1024;
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const UART0_FBRD: u32 = 0x3F20_1028;
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const UART0_CR: u32 = 0x3F20_1030;
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const UART0_CR_UARTEN: u32 = 1 << 0;
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const UART0_CR_TXE: u32 = 1 << 8;
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const UART0_LCRH: u32 = 0x3F20_102c;
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const UART0_LCRH_FEN: u32 = 1 << 4;
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const UART0_LCRH_WLEN: u32 = 11 << 5;
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struct Uart;
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impl Write for Uart {
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fn write_str(&mut self, s: &str) -> fmt::Result {
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for byte in s.bytes() {
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unsafe {
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while core::ptr::read_volatile(UART0_FR as *const u32) & UART0_FR_TXFF != 0 {}
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core::ptr::write_volatile(UART0_DR as *mut u32, byte as u32);
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}
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}
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Ok(())
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loop {
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uart::print("Panic");
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}
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}
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@@ -54,77 +24,23 @@ pub extern "C" fn _start() -> ! {
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#[no_mangle]
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fn main() {
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configure_uart();
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delay(50000);
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let mut uart = Uart {};
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uart::configure_uart();
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// Delay so clock speed can stabilize
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unsafe { delay(50000) }
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uart::print("Hello World!\n");
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loop {
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writeln!(uart, "Hello World!");
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pull_up_gpio47();
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unsafe { delay(10_000_000) } // ~0.5s
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pull_down_gpio47();
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unsafe { delay(10_000_000) }
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}
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}
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pub fn configure_uart() {
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let baud_div_times_64 = (UART_CLK * 4) / BAUD;
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let ibrd = baud_div_times_64 / 64;
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let fbrd = baud_div_times_64 % 64;
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unsafe {
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uart_enable(false);
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uart_fifo_enable(false);
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core::ptr::write_volatile(UART0_IBRD as *mut u32, ibrd);
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core::ptr::write_volatile(UART0_FBRD as *mut u32, fbrd);
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uart_set_lcrh(0b11, true);
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// Enable transmit and uart
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let mut cr = core::ptr::read_volatile(UART0_CR as *mut u32);
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cr |= UART0_CR_UARTEN | UART0_CR_TXE;
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core::ptr::write_volatile(UART0_CR as *mut u32, cr);
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}
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}
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fn uart_enable(enable: bool) {
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unsafe {
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let mut cr = core::ptr::read_volatile(UART0_CR as *mut u32);
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if enable {
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cr |= UART0_CR_UARTEN;
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} else {
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cr &= !UART0_CR_UARTEN;
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}
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core::ptr::write_volatile(UART0_CR as *mut u32, cr);
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}
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}
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fn uart_fifo_enable(enable: bool) {
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unsafe {
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let mut lcrh = core::ptr::read_volatile(UART0_LCRH as *mut u32);
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if enable {
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lcrh |= UART0_LCRH_FEN;
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} else {
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lcrh &= !UART0_LCRH_FEN;
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}
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core::ptr::write_volatile(UART0_LCRH as *mut u32, lcrh);
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}
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}
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fn uart_set_lcrh(wlen: u32, enable_fifo: bool) {
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unsafe {
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let mut value = (wlen & 0b11) << 5;
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if enable_fifo {
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value |= UART0_LCRH_FEN;
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}
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core::ptr::write_volatile(UART0_LCRH as *mut u32, value);
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}
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}
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fn delay(count: u32) {
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unsafe fn delay(count: u32) {
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for _ in 0..count {
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// Prevent compiler optimizing away the loop
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core::sync::atomic::spin_loop_hint();
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core::arch::asm!("nop");
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}
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}
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