Introduce Logger trait

src/peripherals/uart.rs

@@ -3,7 +3,7 @@ use core::{
     fmt::{self, Write},
 };
 
-use crate::{mmio_read, mmio_write};
+use crate::{println, read_address, write_address};
 
 const BAUD: u32 = 115200;
 const UART_CLK: u32 = 48_000_000;
@@ -18,35 +18,14 @@ const UART0_FBRD: u32 = 0x3F20_1028;
 
 const UART0_CR: u32 = 0x3F20_1030;
 const UART0_CR_UARTEN: u32 = 1 << 0;
+
+const UART0_CR_LBE: u32 = 1 << 7;
 const UART0_CR_TXE: u32 = 1 << 8;
+const UART0_CR_RXE: u32 = 1 << 9;
 
 const UART0_LCRH: u32 = 0x3F20_102C;
 const UART0_LCRH_FEN: u32 = 1 << 4;
 
-pub struct Uart;
-
-impl Write for Uart {
-    fn write_str(&mut self, s: &str) -> core::fmt::Result {
-        for byte in s.bytes() {
-            while (mmio_read(UART0_FR) & UART0_FR_TXFF) != 0 {
-                unsafe { asm!("nop") }
-            }
-            mmio_write(UART0_DR, byte as u32);
-        }
-        // wait till uart is not busy anymore
-        while ((mmio_read(UART0_FR) >> 3) & 0b1) != 0 {}
-        Ok(())
-    }
-}
-
-pub fn _print(args: fmt::Arguments) {
-    let _ = Uart.write_fmt(args);
-}
-
-pub fn _print_str(st: &str) {
-    let _ = Uart.write_str(st);
-}
-
 /// Initialize UART peripheral
 pub fn uart_init() {
     let baud_div_times_64 = (UART_CLK * 4) / BAUD;
@@ -55,23 +34,25 @@ pub fn uart_init() {
     let fbrd = baud_div_times_64 % 64;
 
     uart_enable(false);
-    uart_fifo_enable(false);
+    uart_fifo_enable(true);
 
-    mmio_write(UART0_IBRD, ibrd);
-    mmio_write(UART0_FBRD, fbrd);
+    unsafe {
+        write_address(UART0_IBRD, ibrd);
+        write_address(UART0_FBRD, fbrd);
+    }
 
     uart_set_lcrh(0b11, true);
 
-    // Enable transmit and uart
-    let mut cr = mmio_read(UART0_CR);
-    cr |= UART0_CR_UARTEN | UART0_CR_TXE;
+    // Enable transmit, receive and uart
+    let mut cr = unsafe { read_address(UART0_CR) };
+    cr |= UART0_CR_UARTEN | UART0_CR_TXE | UART0_CR_RXE;
 
-    mmio_write(UART0_CR, cr);
+    unsafe { write_address(UART0_CR, cr) };
 }
 
 /// Enable UARTEN
 fn uart_enable(enable: bool) {
-    let mut cr = mmio_read(UART0_CR);
+    let mut cr = unsafe { read_address(UART0_CR) };
 
     if enable {
         cr |= UART0_CR_UARTEN;
@@ -79,12 +60,12 @@ fn uart_enable(enable: bool) {
         cr &= !UART0_CR_UARTEN;
     }
 
-    mmio_write(UART0_CR, cr);
+    unsafe { write_address(UART0_CR, cr) };
 }
 
 /// Enable UART FIFO
 fn uart_fifo_enable(enable: bool) {
-    let mut lcrh = mmio_read(UART0_LCRH);
+    let mut lcrh = unsafe { read_address(UART0_LCRH) };
 
     if enable {
         lcrh |= UART0_LCRH_FEN;
@@ -92,7 +73,7 @@ fn uart_fifo_enable(enable: bool) {
         lcrh &= !UART0_LCRH_FEN;
     }
 
-    mmio_write(UART0_LCRH, lcrh);
+    unsafe { write_address(UART0_LCRH, lcrh) };
 }
 
 /// Set UART word length and set FIFO status
@@ -101,5 +82,24 @@ fn uart_set_lcrh(wlen: u32, enable_fifo: bool) {
     if enable_fifo {
         value |= UART0_LCRH_FEN;
     }
-    mmio_write(UART0_LCRH, value);
+    unsafe { write_address(UART0_LCRH, value) };
+}
+
+pub fn read_uart_data() {
+    println!(
+        "{:?}",
+        (unsafe { read_address(UART0_DR) } & 0xFF) as u8 as char
+    );
+}
+
+pub fn write_str(s: &str) -> core::fmt::Result {
+    for byte in s.bytes() {
+        while (unsafe { read_address(UART0_FR) } & UART0_FR_TXFF) != 0 {
+            unsafe { asm!("nop") }
+        }
+        unsafe { write_address(UART0_DR, byte as u32) };
+    }
+    // wait till uart is not busy anymore
+    while ((unsafe { read_address(UART0_FR) } >> 3) & 0b1) != 0 {}
+    Ok(())
 }